1. Field of the Invention
The present invention relates to digital computers in general, and to computer memory organization in particular. More particularly still, it relates to organization and architecture of cache-memory systems.
2. Prior Art of the Invention
The closest prior art known to the present invention is disclosed in detail in Motorola Inc.'s Users Manual of an integrated circuit known as the MC88200 cache/memory management unit or CMMU. This manual is incorporated herein by reference.
An excellent background paper on the general subject of the present invention by Alan Jay Smith is entitled "Problems, Directions and Issues in Memory Hierarchies" published in the Proceedings of the Eighteenth Annual Hawaii International Conference on System Sciences, 1985. Section 2 of this paper concerns cache memories and is particularly relevant.
Another important background paper by the abovementioned author entitled "Line (Block) Size Choice for CPU Cache Memories" was published Sep. 9, 1987, in the IEEE Transactions On Computers, Vol. C-36, No. 9.
Cache memories temporarily hold portions of the contents of the main system memory which hopefully have a high probability of current use by the CPU or processor. In practice, the cache memory holds recently used contents of main memory. Thus the three basic performance parameters are "hit access time" "miss access time" and "hit ratio." Hit access time is the time to read or write cache memory, when the data is in the cache memory. Miss access time is the time to read main memory when the requested word is not in the cache memory. Hit ratio is the probability of finding the target data in the cache, and directly affects memory traffic making memory or bus bandwidth a critical and limiting resource in RISC (Reduced Instruction Set Computer) microprocessor systems (Smith, 1985).
Memory traffic consists of two components: fetch traffic and write or copyback traffic. The memory fetch traffic increases with line size in the cache, while generally the "miss ratio" (opposite of "hit ratio") declines with increasing line size. Memory traffic also increases with miss ratio.